The present invention relates to a semiconductor memory device, and more particularly to a circuit for controlling a self-refresh period to determine the period of the self-refresh operation in the semiconductor memory device.
Generally, the refresh operation should be continuously performed during the stand-by mode of the memory device that requires the refresh operation to keep data stored in the memory cell of a DRAM device (DRAM: Dynamic Random Access Memory). The refresh operation used for such an object is called "self-refresh". Recently, the power supply voltage of the memory device lowers, so that a current consumption therein must be reduced. Accordingly, the self-refresh operation should be performed with the minimum current consumption. In order to reduce the current consumption for the self-refresh operation, it is desirous to perform the self-refresh operation with the longest period as long as the data retention time of the memory cell in the memory device is satisfied. According to this fact, the period control circuit for the self-refresh operation that can program the period of the refresh operation up to an optimum level is widely used. The period of the self-refresh operation is determined by selecting a pulse train having the longest period to satisfy a data retention time among a number of pulse trains output from a timer as a master clock, after measuring the data retention time of the memory cell in the memory device. The preferred embodiment of such an art is disclosed in detail in Korea patent application No. 93-10315 filed by the same applicant.
In general, the data retention capability of the memory cell is closely related with the level of a power supply voltage and an ambient temperature. That is, if the power supply voltage lowers or if the ambient temperature rises, the data retention capability of the memory cell is deteriorated. Therefore, the refresh operation should be more frequently performed when the power supply voltage is low. Further, the refresh operation should be more frequently performed when the ambient temperature is high. The period control circuit for controlling the self-refresh operation of which period is variable according to the variation of the ambient temperature, is disclosed in the pages 43 and 44 of a publication entitled "SYMPOSIUM ON VLSI CIRCUITS DIGEST OF TECHNICAL PAPERS" published in 1993. According to such an art, the variation of the ambient temperature is detected by using a polysilicon resistor and a well resistor having different resistance-temperature coefficients from each other, and a differential amplifier that is capable of sensing the voltage difference generated between the polysilicon resistor and the well resistor. Further, according to the above mentioned fact, the period of the self-refresh operation is controlled by selecting one of the timers which output predetermined different period pulse trains suitable for the level of the ambient temperature.
However, even if the conventional self-refresh period control circuit controls the period of the refresh operation responding to the ambient temperature of the memory device, the circuit can't control the period of refresh operation responding to the variation of the power supply voltage provided to the memory device.
In addition, the conventional self-refresh period control circuit has the problem that it is difficult to obtain the master clock having a period which approximates to the data retention time of the memory cell. That is, after the conventional timer circuit generates a number of pulse trains having different periods from each other(for example, 2 .mu.s, 4 .mu.s, . . . 128 .mu.s, 256 .mu.s) by frequency-dividing the pulse train output from an oscillator, the timer circuit selects one of the pulse trains as the self-refresh master clock. Since each pulse train has the relationship of the frequency-dividing, the timer circuit can't select a specific pulse train having an appropriate period between any one period and the next period(for example, between the 128 .mu.s and the 256 .mu.s) as the master clock. Further, to form the pulse train having the appropriate period, even if the specific period can be selected as the master clock, another complicated timer circuit is necessitated in the conventional art.